An increasing need to form planar surfaces in semiconductor device fabrication has led to the development of process technology known as chemical-mechanical-polishing (CMP). In CMP processes, semiconductor substrates are rotated against a polishing pad in the presence of an abrasive slurry. Most commonly, the layers to be planarized in semiconductor devices are electrically insulating layers overlying active circuit devices, such as SiO.sub.2, PSG (phosphorus silicate glass) or BPSG (boron-doped PSG), and metal interconnect layers or metal vias, such as those made from aluminum, copper, or tungsten. As the substrate is rotated against the polishing pad, the abrasive force polishes the surface of the exposed insulating or metal layers. Additionally, chemical compounds within the slurry undergo a chemical reaction with the components of the exposed layers to enhance the rate of removal. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than another. The ability to control the selectivity of a CMP process and the effectiveness of a CMP process in planarizing a given film has led to its increased use in the fabrication of complex integrated circuits.
CMP is especially of interest as a process to form conductive plugs or interconnects within semiconductor devices. Plugs are used to vertically connect various conductive members or regions within each device, including diffusion regions, gate electrodes, metal lines, and the like. In a typical plug formation process using CMP, an insulating layer is deposited over active circuitry of a device. The insulating layer is then lithographically patterned and etched to create substantially vertical-walled openings in the insulating layer which expose underlying conductive members or regions to be contacted. A blanket layer of metal is then deposited, thereby filling the openings and covering the entire device surface. CMP is used to polish back the metal layer and portions of the insulating layer so that the resulting device surface is planar, and so that the metal is removed from all portions of the device except within the openings of the insulating layer. These metal filled openings are referred to as plugs.
Tungsten is an attractive metal for use in creating conductive plugs. Unlike aluminum, tungsten can be chemically vapor deposited (CVD) onto a substrate so that vertical-wall openings within an insulating layer will be completely filled. Aluminum is typically sputter deposited. Sputter deposition is unable to completely fill steep, vertical-wall openings, resulting in what is sometimes referred to as voids. The advantage of having the openings in the insulating layer completely filled, resulting in reliable conductive plugs, outweighs the fact that tungsten metal is more resistive than aluminum.
To form tungsten plugs, many semiconductor manufacturers employ reactive ion etch (RIE) techniques. After a blanket layer of tungsten is deposited, filling any opening in an underlying insulating layer, the layer is etched using RIE. RIE techniques are well developed in etching tungsten, but these techniques have several drawbacks. One problem is the degree of overetch required to remove barrier and adhesions layers (such as titanium and titanium nitride) which are often present under a tungsten layer in a semiconductor device resulting in a recessed tungsten plug within the opening. In other words, to clear titanium and titanium nitride from the surface of the insulating layer, the tungsten within the plug opening becomes recessed such that the plugs are not planar with the adjacent insulating layer. An additional problem associated with RIE is that the etches tend to open seams in the metal within each plug opening. In depositing metal into openings in an insulating layer using CVD metal deposition, metal deposits from the sidewalls of the opening inward, resulting in a seam in the metal located near the center of the opening. Upon etching this metal using RIE, the etch attacks the seam area, creating possible reliability problems in the resulting metal plugs. A further disadvantage to the use of RIE in conjunction with forming tungsten plugs is a high particulate level which leads to defects in the semiconductor devices.
For the reasons provided above, it is apparent that CMP would be an attractive alternative to current processes for forming tungsten plugs which use RIE. However, existing CMP techniques for polishing tungsten also have significant drawbacks. For instance, slurries which have been used to polish tungsten typically have very low pHs. The high acidity of these slurries attacks and stains the CMP equipment, particularly tubs, and creates material handling concerns. Furthermore, CMP techniques used to polish tungsten often have very slow polishing rates which are not suitable for a manufacturing environment. Accordingly, a need for an improved CMP technique, and particularly one which etches tungsten, would be beneficial.